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3D Network-on-Chips Modeling and Optimization
NoC design, synthesis, and implementation
The research group aims at optimizing the design of on-chip interconnects for complex SoC systems. Using bio-inspired optimization algorithms, we study the impact of changing various design parameters on the system performance to find the optimum architecture of the on-chip network. The objectives are to maximize processor speed & system reliability and minimize energy consumption & implementation area.
Group Coordinator: Dr. Haytham El Miligi
Email: helmiligi@tru.ca
Phone: 250-828-5230
